AD73322,pdf,datasheet

The AD73322 and AD73322L are dual, front-end processor for general-purpose applications including speech and telephony. They feature two 16-bit A/D conversion channels and two 16-bit D/A conversion channels. Each channel provides 77 dB signal-to-noise ratio over a voiceband signal bandwidth. The AD73322 power-supply range includes 3 V and 5 V operation, the L version operates from 3 V only. They also feature an input-to-output gain network in both the analog and digital domains. The networks are on both codecs and can be used for impedance matching or scaling when interfacing to Subscriber Line Interface circuits (SLICs).

The A/D and D/A conversion channels feature programmable input/output gains with ranges of 38 db and 21 dB respectively. An on-chip reference voltage is included to allow single supply operation. This reference is programmable to accommodate either 3 V or 5 V operation.

The sampling rate of the codecs is programmable with four separate settings offering 64, 32, 16 and 8 ksps sampling rates. The master clock is 16.384 MHz.

A serial port (SPORT) allows easy interfacing of single or cascaded devices to industry standard DSP engines. The SPORT transfer rate is programmable to allow interfacing to both fast and slow DSP engines.

The AD73322 and AD73322L are available in 28-lead SOIC and 44-lead LQFP packages.